Volume & Issue no: Volume 6, Issue 2, March - April 2017
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Title: |
AN ASYNCHRONOUS LOW POWER VITERBI DECODER |
Author Name: |
KANDULA RAMA RAO,R.JAHNAVI, CH.JAYASRI, B.KUNDANA VALLI, K.TRIVENI |
Abstract: |
Abstract
This project manages Error adjusting systems in correspondence arrange. For deciphering of convolution codes at the collector side, Viterbi decoder is frequently used to guarantee that information achieve goal accurately. Forward Error Correction (FEC) plans are a fundamental segment of remote correspondence frameworks. The point of this venture is to diminish the power utilization roar 40mW and deferral is under 5ns. The non-concurrent configuration is naturally information driven and dynamic while doing valuable work where control sparing with worthy speed punishment is gotten. X-power analyzer device is utilized to quantify control utilization. For the Asynchronous outline, Bundled information convention is utilized as a part of this paper .The non-concurrent configuration is based upon PCHB, WCHB , to anticipate superfluous drifters and stay away from postponement in the circuits .The proposed design can be acknowledged by offbeat Viterbi Decoder having imperative length, K of 3 and a code rate (k/n) of 1/2 utilizing Verilog HDL. The equipment portrayal dialect Verilog HDL is utilized to depict the outline. The plan is orchestrated and reenacted utilizing Xilinx 14.6 programming.
Keywords: Convolution codes, FEC, survivor path, Trace Back (TB), Viterbi Decoder , Asynchronous Viterbi Decoder,xillinx 14.6software. |
Cite this article: |
KANDULA RAMA RAO,R.JAHNAVI, CH.JAYASRI, B.KUNDANA VALLI, K.TRIVENI , "
AN ASYNCHRONOUS LOW POWER VITERBI DECODER" , International Journal of Emerging Trends & Technology in Computer Science (IJETTCS) ,
Volume 6, Issue 2, March - April 2017 , pp.
092-096 , ISSN 2278-6856.
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